1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method for the same. More particularly, the present invention relates to a semiconductor memory device having at least two divided charge-storage layers and a control gate, and a manufacturing method for the same.
2. Description of the Related Art
Non-volatile semiconductor memory devices including a flash memory are in use in a variety of fields such as computer, communication, measurement equipment, automatic control apparatus, consumer electronics for private use and the like as compact data-recording media having a large capacity. Accordingly, demand for non-volatile memories having a larger capacity and available at a lower cost is very high.
However, the capacity of a so-called planar type memory wherein semiconductor memory devices (memory cells) are formed in a plane on a semiconductor substrate is restricted by the minimum processing dimension (feature size) on which the resolution limit of photolithography technology is imposed. Under such circumstances, multi-value technology and three-dimensional technology of a memory cell are studied as technologies for enabling the integration in the next generation without relying on an improvement in the photolithography technology.
The multi-value technology is roughly divided into two types of technologies: threshold-value control type technology to set three or more threshold-value distributions in one memory cell; and charge-storage-region divided type technology to provide, in one memory cell, divided regions for independently storing a charge. Examples of the former threshold value control type technology include floating gate type technology, while known as examples of the latter charge-storage-region divided type technology are NROM type technology (see, for example, Japanese Unexamined Patent Publication No. 2001-77220), divided floating gate type technology (see, for example, Japanese Patent No. 2870478) and the like technology.
FIG. 25 shows a schematic cross section of a NROM type memory array which is a drawing contained in Japanese Unexamined Patent Publication No. 2001-77220, a publication disclosing the charge-storage-region divided type technology. In the NROM type memory array, memory cells each including a charge-storage layer made of an oxide film/nitride film/oxide film (ONO film) are arranged in the form of an array. In FIG. 25, reference numeral 1 denotes a semiconductor substrate, 12 a bitline, 15 a channel, 17 a nitride layer, 18 an oxide layer, 20 another oxide layer, 50 bitline-like oxide, 51 sidewall oxide and 60 a polysilicon wordline.
Referring to FIG. 25, two regions for holding a charge can be arranged in the charge-storage layer made of the oxide film/nitride film/oxide film (ONO film), and two-bit data can be stored in one memory cell.
In the multi-value technology, a capacity of two-bit or more data per one memory cell is secured with the same processing dimensions as those of a memory cell that has a capacity of one-bit data per one memory cell, thereby overcoming the capacity restriction due to the resolution limit of the photolithography technology.
In the three-dimensional technology of a memory cell, on the other hand, memory cells can be placed also perpendicularly to the direction to a substrate to provide, as is the case with the multi-value technology, a capacity equal to or greater than that of a planar type memory with the same processing dimensions as those of the planar type memory. Further, this technology in which the precision required for the control of the amount of charge is the same as that required in the planar type memory can provide a further increased capacity with an increase in the number of memory cells to be placed in the direction perpendicular to the substrate.
In the multi-value technology of a memory cell, the planar technology is utilized, and a capacity of two-bit or more data is secured per one memory cell. In the threshold value control type multi-value technology and charge-storage-region divided type multi-value technology in which the planar technology is utilized as mentioned above, however, memory cells are arranged in a plane. In these technologies, with a reduction in memory cell area, the distance between the source and drain regions decreases, inducing a punch-through phenomenon. This hinders the scaling down. For this reason, the multi-value technology is not appropriate for high integration. Further, in the multi-value technology, the channel width also decreases with a reduction in memory cell area, causing an apprehension about a reduction in drive voltage and thus about a decrease in read out operation speed.
In the three-dimensional technology, memory cells are arranged in a direction perpendicular to a semiconductor substrate surface in order to secure a capacity equal to or greater than that of a planar type memory. In this technology, however, as a greater number of memory cells are stacked in multiple stages, a greater number of manufacturing steps are required, causing an increase in manufacturing costs, an extension in the length of period for manufacture and a decrease in yield. Further, due to differences in thermal hysteresis among stages, the memory cells manufactured vary in the qualities of a tunnel film as an element of a memory cell and in the profile of a diffusion layer. Consequently, cell characteristics vary.